1. Field of the Invention
The present invention generally relates to the fabrication of semiconductor devices and to polishing and planarizing substrates.
2. Background of the Related Art
Reliably producing sub-quarter micron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the fringes of circuit technology are pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias, contacts, lines, and other interconnects. Reliable formation of these interconnects is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
Multilevel interconnects are formed by the sequential deposition and removal of materials from the substrate surface to form features therein. As layers of materials are sequentially deposited and removed, the uppermost surface of the substrate may become non-planar across its surface and require planarization prior to further processing. Planarizing a surface, or “polishing” a surface, is a process where material is removed from the surface of the substrate to form a generally even, planar surface. Planarization is useful in removing excess deposited material and removing undesired surface topography and surface defects, such as rough surfaces, agglomerated materials, crystal lattice damage, scratches, and contaminated layers or materials to provide an even surface for subsequent processing.
Chemical mechanical planarization, or chemical mechanical polishing (CMP), is a common technique used to planarize substrates. In conventional CMP techniques, a substrate carrier or polishing head is mounted on a carrier assembly and positioned in contact with a polishing media in a CMP apparatus. The carrier assembly provides a controllable pressure to the substrate urging the substrate against the polishing media. The substrate and polishing media are moved in a relative motion to one another.
A polishing composition is provided to the polishing media to effect chemical activity in removing material from the substrate surface. The polishing composition may contain abrasive material to enhance the mechanical activity between the substrate and polishing media. Thus, the CMP apparatus effects polishing or rubbing movement between the surface of the substrate and the polishing media while dispersing a polishing composition to effect both chemical activity and mechanical activity. The chemical and mechanical activity removes excess deposited materials and planarizes a substrate surface.
Chemical mechanical polishing may be used in the fabrication of shallow trench isolation (STI) structures. STI structures may be used to separate transistors and components of a transistor, such as source/drain junctions or channel stops, on a substrate surface during fabrication. STI structures can be formed by depositing a series of dielectric materials and polishing the substrate surface to remove excess or undesired dielectric materials. An example of a STI structure fabrication sequence includes depositing a silicon nitride layer on an oxide layer formed on a doped silicon substrate surface, patterning and etching the substrate surface to form a feature definition, depositing a silicon oxide fill of the feature definitions, and polishing the substrate surface to remove excess silicon oxide to form a feature. The silicon nitride layer may perform as a hard mask during etching of the features in the substrate and/or as a polishing stop during subsequent polishing processes. Such STI fabrication processes require polishing the silicon oxide layer to the silicon nitride layer with a minimal amount of silicon nitride removed during the polishing process in order to prevent damaging of the underlying materials, such as oxide and doped silicon.
The STI substrate is typically polished using a conventional polishing media and an abrasive containing polishing slurry. However, polishing STI substrates with conventional polishing media and abrasive containing polishing slurries has been observed to result in overpolishing of the substrate surface or the formation of recesses in the STI features and other topographical defects such as microscratches on the substrate surface. This phenomenon of overpolishing and forming recesses in the STI features is referred to as dishing. Dishing is also used to refer to overpolishing and forming recesses in other types of features. Dishing is highly undesirable because dishing of substrate features may detrimentally affect device fabrication by causing failure of isolation of transistors and transistor components from one another, resulting in short-circuits. Additionally, overpolishing of the substrate may also result in oxide loss and exposure of the underlying oxide to damage from polishing or chemical activity, which detrimentally affects device quality and performance.
Dishing is particularly likely to occur during the polishing of a substrate having a non-uniform distribution of features on the substrate surface or during the polishing of a substrate having wide features, e.g. about 100 μm. An example of a type of substrate, e.g., a STI substrate, that has a non-uniform distribution of features is a polysilicon substrate having storage cells and capacitor plates of flash memory devices for sub 0.18 μm technology, as shown in FIG. 1. The substrate 10 comprises a layer of polysilicon 12 formed over oxide components 14. The region 13 of the substrate 10 above the oxide components 14 is referred to as the field. Typically, the field is higher than the region 15 of the substrate 10 above the trenches 22 between the oxide components 14. The array 18 of the storage or memory cells has a high density of features and the area 16 of the capacitor plates has a low density of features. When conventional polysilicon CMP is performed on such a substrate, the removal rate of material from the substrate surface in the high density area is lower than the removal rate in the low density area. In order to planarize the substrate surface in the high density area, the substrate must be polished to an extent that results in overpolishing, and thus, dishing, in the low density area. An example of a polysilicon substrate that has experienced dishing from CMP is shown in FIG. 2. The line 20 shows the amount of dishing experienced in a trench 22 of the substrate. Thus, dishing may also be described as the removal of too much material, such as polysilicon, from the region of the substrate above the trenches in the substrate.
Therefore, there exists a need for a method and a CMP composition which facilitates the removal of polysilicon from a substrate with minimal or reduced dishing. In particular, there exists a need for a method and a CMP composition which facilitates the removal of polysilicon from a substrate having a non-uniform density of features and/or large feature sizes.